The present invention relates to a register access circuit used in a microcomputer or the like, and a data processing method in the register access circuit when an interruption request signal is output from an interruption request circuit connected to the register access circuit to a central processing unit.
For example, a microcomputer used in a system having a construction as shown in FIG. 7 is composed of a large-scale integrated circuit (hereinafter referred to as an LSI) and a central processing unit (hereinafter referred to as a CPU), and the CPU can access a register inside the LSI via an interface circuit which satisfies a predetermined specification. Further, the CPU is connected to an interruption request circuit from the LSI, although it is not shown in the figure.
First of all, the CPU access to the register will be briefly described. The CPU outputs address information and a write enable signal or a read enable signal to the LSI to request access to the register inside the LSI. Then, the LSI outputs data to the CPU according to the input address information and the write enable signal or the read enable signal. Alternatively, the LSI captures data in the register so that the CPU can read or write the contents of the register inside the LSI.
Next, the operation of the interruption request circuit will be briefly described. The interruption request circuit receives the internal status of the LSI (e.g., end of data processing, generation of an error, a request to the CPU, etc.) as an interruption request signal, from each of circuit blocks inside the LSI. Then, the interruption request circuit appropriately outputs the received interruption request signal to the CPU. In this way, the CPU can know the internal status of the LSI by processing the interruption request signal.
On receipt of the interruption request, the CPU interrupts the processing in progress (main routine) to handle the interruption request. Next, the CPU accesses data decoded in a predetermined address to recognize the cause of the interruption. After recognizing the cause of the interruption, the CPU performs a predetermined process on the LSI. When this process has ended, the CPU clears the interruption cause and returns to the main routine.
However, in the LSI connected to the CPU, there exists a block performing data processing independently of the operation of the CPU. When an error or the like occurs in the data processing performed in this block, this block sometimes outputs an interruption request signal to the CPU independently of the CPU""s operation to detect the states of flip-flops.
For example, it is assumed that the instruction word length of the CPU is not equal to the width of an internal bus line of the LSI connected to the CPU, like that the instruction word length of the CPU is 16 bits while the bus width is 32 bits. In this case, when the CPU writes only 16 bits of data in the LSI, if an interruption request signal is output to the CPU from a block performing data processing independently of the operation of the CPU, the CPU performs interruption processing on the LSI. At this time, writing of data to the register has not yet ended because the LSI does not output a write enable signal to the register until 32 bits of data are written in it. That is, register access is undesirably performed although only 16 bits of data are written in the LSI. As the result, the 16 bits of data which have already been written in the LSI are overwritten, and the 16 bits of data are erased.
In this way, even while the CPU accesses the register of the LSI with the result of the CPU""s detecting the flip-flop states being xe2x80x9cno interruption requestxe2x80x9d, there is a possibility that a block having no relation with the operation of the CPU outputs an interruption request signal to the CPU and, in this case, there occurs a problem that the data which are being written in the LSI are erased.
The above-described problem has conventionally been solved by adopting the following methods: a method of making the bus width of the LSI equal to the instruction word length of the CPU, such as using an LSI whose internal bus width is equal to the instruction word length of the CPU; a method of employing an internal bus width changing switch, such as providing the LSI with an internal bus width changing switch for changing the internal bus width of the-LSI according to a variety of instruction word lengths of the CPU; and a method of dealing with the problem at the software end of the CPU, such as providing the CPU with software which gives priority to the main routine of the CPU even when an interrupt request signal is generated and does not perform interruption processing until this main routine is ended.
However, in the method of making the bus width of the LSI equal to the instruction word length of the CPU, it is necessary to change the CPU according to every LSI to be connected and, therefore, the software properties in the past cannot be effectively utilized. Hence, this method is not sufficient to solve the above-mentioned problem.
Further, the method of employing an internal bus width changing switch has the following drawback. Although an ordinary LSI is designed so as to have a wide internal bus width to increase the data transfer rate, if the internal bus width of the LSI is changed according to every instruction word length of the CPU, it is difficult to keep the data transfer at a high rate, resulting in degraded performance of hardware. Further, a circuit block for changing the internal bus width is required, whereby the circuit becomes redundant and, further, the circuit scale increases. Therefore, this method is not sufficient to solve the above-mentioned problem.
In the method of dealing with the problem at the software end of the CPU, the data processing rate is determined by a part of the software where the rate is lowest, and this interferes with parallel processing between the software and the hardware, resulting in difficulty in realizing versatile software. Therefore, this method is not sufficient to solve the problem.
Furthermore, there is a method of continuously making access adapted to the internal bus width of the LSI to avoid the above-mentioned problem. In this method, however, with respect to an interruption request which is input asynchronously, the CPU""s recognition of the interruption and the processing thereof are determined not by the instruction word length of the CPU but by the internal bus width of the LSI and, therefore, overhead up to the interruption processing occurs, whereby the interruption processing to the hardware is delayed.
This problem will be described in more detail by using FIGS. 6(a) and 6(b) for explaining overhead of firmware. Although firmware as shown in FIG. 6(b) is originally desired, actually recognition of interruption delays by a period of overhead as shown in FIG. 6(a). So, when an interruption is generated, the hardware which has outputted the instruction of interruption is in the stopped state until the interruption is recognized, received and processed, and therefore it takes long time until interruption processing is completed. That is, the period during which the hardware is in the stopped state increases, whereby the data transfer rate cannot be increased.
The present invention is made to solve the above-described problems and has for its object to provide a register access circuit which can maximize the period during which a CPU and an LSI operate in parallel by constructing the register access circuit so that it can rapidly accept and handle interruption processing instructed by hardware, i.e., by reducing the overhead time until the interruption processing, even when the LSI connected to the CPU has a bus width different from the instruction word length of the CPU, and which realizes high-speed data transfer by increasing the data transfer efficiency, without necessity of making the CPU""s instruction word length equal to the LSI""s bus width, providing an internal bus width changing switch, and dealing with the problem at the CPU""s software end such that access adapted to the LSI""s internal bus width is continuously performed.
Another object of the present invention is to provide a data processing method using the register access circuit.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided a register access circuit comprising, at least, first data holding means having a plurality of data holding circuits; second data holding means having at least one data holding circuit, connected to some of the data holding circuits in the first data holding means; and data output selecting means for selecting data held by some of the data holding circuits in the first data holding means, or data held by some of the data holding circuits in the second data holding means. In this circuit, when an interruption request signal is asserted to the register access circuit, part of the data held by the first data holding means is given to the second data holding means, and when the interruption request signal is negated, the data output selecting means selects the data of the second data holding means to output the data.
According to a second aspect of the present invention, in the above-described register access circuit, when the number of the data holding circuits possessed by the first data holding means is n (n: natural number), the number of the data holding circuits possessed by the second data holding means is one selected from (n/4), (n/2), and (3xc3x97n/4).
According to a third aspect of the present invention, in the above-described register access circuit, the number n of the data holding circuits possessed by the first data holding means is 32.
According to a fourth aspect of the present invention, in the above-described register access circuit, the number of the data holding circuits possessed by the second data holding means is 16.
According to a fifth aspect of the present invention, there is provided a register access circuit comprising, at least, 32 pieces of first-stage flip-flops; 16 pieces of second-stage flip-flops connected to 16 pieces of the first-stage flip-flops; 16 pieces of selector circuits for giving part of data held by the first-stage flip-flops to the second-stage flip-flops; a logic gate; and 32 pieces of gate circuits for selecting data held by some of the first-stage flip-flops or data held by some of second-stage flip-flops to output the data. In this circuit, when an interruption request signal is asserted to the register access circuit, part of the data held by the first-stage flip-flops is given to the second-stage flip-flops by using the selector circuits, and when the interruption request signal is negated, the selector circuits select the data held by the second-stage flip-flops and output the data through the gate circuits.
According to the above-described register access circuit of the present invention, even when the instruction word length of a CPU connected to an LSI including the register access circuit is different from the internal bus width of the LSI, data in the LSI is prevented from being erased by interruption processing of the CPU. Further, since the register access circuit of the present invention is provided with the logic circuit which gives the data of the first data holding circuit to the second data holding circuit in response to the interruption request signal and switches the output of the first data holding circuit and the output of the second data holding circuit, there is no necessity of making the CPU""s instruction word length equal to the LSI""s bus width, providing an internal bus width changing switch, or dealing with the problem at the CPU""s software end. So, redundant circuits are dispensed with, resulting in a simple circuit structure. Further, even when the LSI whose bus width is different from the CPU""s instruction work length is connected to the CPU, since the register access circuit is constructed so that it can rapidly accept and handle interruption processing instructed by hardware, i.e., since the overhead time until the interruption processing is reduced, parallel processing between the CPU and the LSI is realized and, furthermore, high-speed data transfer is realized.
According to a sixth aspect of the present invention, there is provided a data processing method using a register access circuit, which is employed in a system comprising: a central processing unit; a register circuit; a register access circuit for accessing the register circuit under control of the central processing unit; and an interruption request circuit connected to the central processing unit. The register access circuit comprises, at least, first data holding means having a plurality of data holding circuits; second data holding means having at least one data holding circuit, connected to some of the data holding circuits in.the first data holding means; and data output selecting means for selecting data held by some of the data holding circuits in the first data holding means or data held by some of the data holding circuits in the second data holding means to output the selected data. The data processing method comprises a first step of giving part of the data held by the first data holding means to the second data holding means when the interruption request circuit outputs an interruption request signal to the central processing unit; and a second step of composition the data held by the second data holding means after the first step with part of the data held by the first data holding means which has not yet been connected to the second data holding means, and outputting the composite data, when the central processing unit ends interruption processing according to the interruption request signal.
According to a seventh aspect of the present, invention, in the above-described data processing method using a register access circuit, when the number of the data holding circuits possessed by the first data holding means in the register access circuit is n (n: natural number), the number of the data holding circuits possessed by the second data holding means is one selected from (n/4), (n/2), and (3xc3x97n/4).
According to an eighth aspect of the present invention, in the above-described data processing method using a register access circuit, the number n of the data holding circuits possessed by the first data holding means in the register access circuit is 32.
According to a ninth aspect of the present invention, in the above-described data processing method using a register access circuit, the number of data holding circuits possessed by the second data holding means in the register access circuit is 16.
According to a tenth aspect of the present invention, there is provided a data processing method using a register access circuit, which is employed in a system comprising: a central processing unit; a register circuit; a register access circuit accessing the register circuit under control of the central processing unit; and an interruption request circuit connected to the central processing unit. The register access circuit comprises, at least, 32 pieces of first-stage flip-flops; 16 pieces of second-stage flip-flops connected to 16 pieces of the first-stage flip-flops; 16 pieces of selector circuits for giving part of data held by the first-stage flip-flops to the second-stage flip-flops; a logic gate; and 32 pieces of gate circuits for selecting data held by some of the first-stage flip-flops or data held by some of second-stage flip-flops to output the data. The data processing method comprises a first step of giving part of the data held by the first data holding means to the second data holding means when the interruption request circuit outputs an interruption request signal to the central processing unit; and a second step of composition the data held by the second data holding means after the first step with part of the data held by the first data holding means which has not yet been connected to the second data holding means, and outputting the composite data, when the central processing unit ends interruption processing according to the interruption request signal.
According to the above-described data processing method of the present invention, it is possible to prevent malfunction of the CPU""s register access when an interruption request is generated during the register access, by utilizing the above-described register access circuit. According to this procedure, even when the instruction word length of the CPU connected to an LSI including the register access circuit is different from the internal bus width of the LSI, data in the LSI is prevented from being erased by interruption processing of the CPU. Further, in the data processing method of the present invention, there is no necessity of making the CPU""s instruction word length equal to the LSI""s bus width, providing an internal bus width changing switch, or dealing with the problem at the CPU""s software, and therefore redundant process steps are dispensed with. Further, even when the LSI whose bus width is different from the CPU""s instruction work length is connected to the CPU, since the register access circuit is constructed so that it can rapidly accept and handle interruption processing instructed by hardware, i.e., since the overhead time until the interruption processing is reduced, parallel processing between the CPU and the LSI is realized and, furthermore, high-speed data transfer is realized.